About me

Piyush Keshri

Engineer, Entrepreneur & Web Developer

I am currently a first year MBA - Class of 2018, student at The Wharton School, University of Pennsylvania. I am interested in Technology, Entrepreneurship and payments (Fin-Tech). I worked as Senior Analog Design Engineer, at Intel Corporation, Santa Clara from 2011-2016. I completed MS(EE) from Stanford University, CA, USA in 2011 and B.Tech(EE) from Indian Institute of Technology Kanpur, India in May'09. My love for engineering have convinced me to pursue interests from Hardware to Software engineering. My innate desire to be a passionate businessman transformed brick-n-mortar family store into multi-employee Omni-channel grocery enterprise, Dilligrocery serving thousands of customers and corporate clients in Delhi, NCR region. I am an enthusiastic Programmer and Web Developer interested in being part of a successful and productive team.

Download Printable Resume

Current Venture

Currently, I am working on an idea, EasyPay for simplifying offline retail in India.

Experience

Things I have been upto that are worth mentioning here :)

Jul. 2016 Apr. 2013

Senior Analog Design Engineer

Intel Corporation, Santa Clara, US

Analog Front End Design for OPIO (On Package I/O Interface) Design team for Xeon PhiTM. Designed Receiver Block - capacitively coupled, bias block, amplifier, offset cancellation. Guided Extensive layout review and critical design challenges.

Intel’s Highest Honor – Intel Architecture Award (IAA)’15 awarded to the entire team for exceptional contributions.

Intel’s 2nd Highest Honor – Division Recognition Award (DRA)’16 awarded for delivering successful product release despite numerous challenges.

Mar. 2013 Jun. 2011

Analog Design Engineer

Intel Corporation, Santa Clara, US

Designed Resistor Compensation block involving Comparator design, Tx, vref Ladder. Worked on clock distribution in Rx/Tx clusters, Sideband Rx & Local Clock Macros. Leveraging scripting languages (Perl,Tcl) in evaluating circuits for corner cases and variations.

Till Date Apr. 2011

Dilligrocery.com

Founder / Developer

Online Grocery Store serving corporate clients and families across Delhi region, India.

Mar,2012 Dec. 2011

Relcy.com

Product Developer, Founding Team

Providing relevant web-content to users based on users’ social-interest graphs.



Internships

Fun I was having outside classes while I was at school!

Sep. 2010 Jun. 2010

Design Intern

National Semiconductor, Santa Clara, US

Analog Front End Design for Bidirectional Communication On 10m coaxial cable @ 3Gbps. Design Blocks - CML Driver, Z-network Replica, Echo Canceller, and Active Equalizer. Application - Automotive Infotainment Systems – Audio, Video HD Displays.

Jul. 2008 May. 2008

Research Intern

University of Michigan, Ann Arbor, US

Analyzed & designed highly Power Efficient CMOS Thyristor based Ring Oscillators. Application: DC-DC converters in Laptop Power Supplies.

Jul. 2007 May. 2007

Research Intern

Prof. Girish Kumar, Indian Institute of Technology Bombay, India

Market analysis of the WiMAX System and Designing of Transceiver Circuit on PCB for the 5-5.9 GHz and 2-3 GHz frequency ranges.

Jun,2006 May. 2006

Summer Intern

Electronics Club, Indian Institute of Technology Kanpur, India

Our team of three students designed a Digital Security Code Lock System using Atmega8 microcontroller, programmed in C as well as Assembly Language which operates on digital lock using the 16bit LCD display.

Talks

Few moments of imparting knowledge on other side of podium!

Oct. 2008

1st Indo-US Research Academy

Pune, India. Mentor:Prof. S.S.K Iyer, EE Dept., IIT Kanpur

"Maximising incident power absorption in multijunction Solar Cells". The project and the presentation is based on determining the optimum band gap of the materials for single/double and triple junction solar cells to maximise the photon absorption by the multi junction solar cells to optimize the efficiency.

→ View report
Dec. 2007

6th Indo-German Winter Academy

IIT Guwahati, India. Mentor:Prof. Heiner Ryssel, University of Erlangen

"Towards Highly Efficient Monolithic DC-to-DC to Converter". The presentation gave an overview on the state-of the-art of monolithic DC/DC converters, with low power, high efficiency, high switching frequency in (MHz) for a completely monolithic integrated switch-mode power converter.

→ View ppt

Education

Hard earned Sweat that resulted in a Degree at last (almost :D ).

May, 2018 (Est.)

Master of Business Administration

The Wharton School, University of Pennsylvania, US

GMAT - 760 (99th Percentile)

Top finalist for Class of 2018 ‘Big Idea’ Innovation tournament

VP Leadership - Cluster Council; Startup Chair - Wharton India Economic Forum; Member of Tech Club, E-Club, FinTech Club

Jun, 2011

Master of Science, Electrical Engineering

Stanford University, US

CGPA - 3.92/4.0

Cleared Qualifiers for PhD Program in Electrical Engineering in Jan. 2011 with Rank 26 at Stanford University and took leave from PhD program.

May, 2009

Bachelor of Technology, Electrical Engineering

Indian Institute of Technology Kanpur, India

CGPA - 9.7/10.0

May, 2005

12th (CBSE)

St. Xavier's School, Delhi

Percentage Obtained: 91.4 %

May, 2003

10th (CBSE)

St. Xavier's School, Delhi

Percentage Obtained: 89.4 %

Projects

Things I have been upto that are worth mentioning here :)

2009-11

Stanford


Design of 5-Bit Time-Interleaved ADC

EE315B,Stanford,Sep'10-Nov'10.

Each ADC operates at 400MS/s and can sample up to 1.6GHz signal. Clocked Bootstrap Switch & Double Tail Latch Type Sense Amplifier based Comparator.

→ View report

Comparative Study of Trans impedance Amplifier

Prof. Boris Murmann, Stanford- Apr’10-May’10

• Analyzed trade-offs for various topologies specifically– Capacitive feedback, Resistive feedback and Integrator-Differentiator approach For MEMS Resonators for GSM Systems.

→ View report

Design of 3.5 GHz Wideband Trans impedance Amplifier

EE214, Stanford- Jan’10-Mar’10

For high speed Optical Communication Systems using 180nm CMOS Technology. Implemented Cherry Hooper Architecture for High Gain & Bandwidth.

→ View report

Analysis and Design of High Frequency Transceiver LNA-Mixer

EE314, Stanford- Apr’10-May’10

For WiFi Chipsets at operating frequency of 2.45GHz & Bandwidth of 200MHz. Power Gain 30dB and IIP3 ~ - 20dBm using 90nm CMOS Technology. Architecture - Inductively Degenerated Cascoded LNA & Double Balanced Active Mixer.

→ View report

VLSI Implementation of DNA Sequencing

EE272, Stanford- Apr’10-May’10

Synthesized, placed and routed complete ASIC design using 90nm CMOS Technology. Employed low power Verilog coding techniques with hardware reusage and parallelism.

→ View report

Hardware Improvements for Micropolygon Rasterization

EE271, Stanford- Sep’09-Nov’09

Optimized throughput & power by 3.5X, using - Triangle Merging, backface Culling. Special Acknowledgement for “Lowest Energy &Minimum Area Optimized Design".

→ View report

Design of High Speed & low power SRAM Memory

EE313, Stanford- Jan’10-Mar’10

Designed a 64kB complete SRAM memory using 45nm CMOS Technology. Significant Techniques – Divided Wordline, partitioned Bitline, variable delay SAE signal.

→ View report

Designing a High Speed Signaling System

EE273, Stanford- Jan’10-Mar’10

To connect line modules in a High Speed Router operating at 40Gbps. Employed a pair of Central Crossbar switches with backplane architecture.

→ View report

Optical Character Recognition for Handwritten Hindi

CS229, Stanford- Sep’10-Dec’10

Various feature extraction and classification algorithms explored. Best results obtained using One-against-All SVM & extracting features using HOG process.

→ View report

Hardware Improvements for Rasterizer Design

EE Dept., Stanford University

The goal of the project is to get a render speed of 500 Million μPolys/sec while consuming as little power and area as possible. The baseline rasterizer provided runs with a clock period of 1.05 ns and has a throughput of 0.083 μPolys/cycle( or 79 Million μPolys/sec). We were able to obtain a throughput of 550 Million μPolys/sec. Hence, our design meets the throughput requirements, has an optimized FOM value and also has power and area dissipation within the specified budget of 300mW and 1mm2 respectively. Our implementation strategy has received the "Lowest Energy Design with Minimum Area Overhead" award within the complete class and have given special presentation over the strategies being followed by us. (NOTE: Video Link for the presentation will be soon uploaded).

→ View report

Amplifier Design for Pore Based Bio-Sensor Chip

Prof. Robert Dutton , EE Dept., Stanford University.EE Dept., Stanford University

The project is based on Designing the amplifier for pore based Bio-Sensor chip with the required specifications (as mentioned in design problem statement). The robust design for the amplifier circuit has been implemented and simulated in the HSPICE. Our design has received the "Best Robust Design with Least Power Consumption" award within the complete class.

→ View report

2005-09

IIT Kanpur


B.Tech Project: Networked Service Request System (NSRS)Networked RFID System (NRS) for Remote Services

Prof. S. Qureshi, EE Dept., IIT Kanpur.IIT Kanpur – July’08-Apr’09

Designed Complete Hardware-Software platform for requesting emergency services. Integrated RFID & GSM Technology with the Central Web Based Database System. Developed complete IVR System & Web Platform to connect to central Database.The project is based on Designing Networked RFID System (NRS) ",which is the extension of the project "Remote Gas Service" which has filed the National patent on April'08. The project is aimed at Designing a networked RFID system which integrates RFID reader & Web interface with the Web based Centralized Database Management System. The system has been extended and has been integrated with the wireless access using GSM modules & also using wired telephone lines to form Interactive voice response system to access Database. The project has been aimed with the objective of implementation in remote and rural areas to provide emergency services through efficient reliable system. The project is soon to be implemented within the campus for initial phase testing.

→ View report

Analysis of High Speed Low Power Flip Flops

Mentor:Prof. S. Qureshi, EE Dept., IIT Kanpur.Prof. Robert Dutton , EE Dept., Stanford University.EE Dept., Stanford University

The project is based on designing the compensation circuit for the CMOS thyristor based Current Starved Ring Oscillator design operating at 100kHz to reduce the Temperature Sensitivity of the circuit. Project is based on the analysis of the performance of different high speed low power flip flops such as Hybrid Latch Flip Flop, Sense Amplifier based Flip Flop, Semi- Dynamic Flip Flop, Master Slave Flip Flop, Clock Gated Master Slave Flip Flop and other modified designs of Sense Amplifier based Flip Flops.

Report Not Available!

Design of Compensation circuit to neutralise Temperature Dependence of the Ring Oscillator Design based on CMOS Thyristor Design

Course Project
Mentor:Prof. S. Qureshi, EE Dept., IIT Kanpur

The project is based on designing the compensation circuit for the CMOS thyristor based Current Starved Ring Oscillator design operating at 100kHz to reduce the Temperature Sensitivity of the circuit. The technology used is 0.18micron.

→ View report , → View ppt

Maximising incident power absorption in multijunction Solar Cells

1st Indo-US Research Academy, Pune, India (07-11th October'08)
Mentor:Prof. S.S.K Iyer, EE Dept., IIT Kanpur

The project and the presentation is based on determining the optimum band gap of the materials for single/double and triple junction solar cells to maximise the photon absorption by the multi junction solar cells to optimize the efficiency.

→ View report

Towards Highly Efficient Monolithic DC-to-DC to Converter

6th Indo-German Winter Academy, Guwahati, India (13th-19th Dec.'07) Mentor:Prof. Heiner Ryssel, University of Erlangen.

Contributed presentation in 6th Indo-German Winter Academy-2007, held from 13th-19th December’07 at IIT Guwahati. The presentation gave an overview on the state-of the-art of monolithic DC/DC converters, with low power, high efficiency, high switching frequency in (MHz) for a completely monolithic integrated switch-mode power converter.

→ View ppt

Dynamics of Mobius Transformations and Image Compression

Prof. G.P. Kapoor, Mathematics Dept., IIT Kanpur

The presentation is based on exploring the dynamics of mobius transformations and image compression technique using fractals. Fractal Image Compression technique can be used for Image Compression effectively reduces size of the image file from few MHz to few kHz.

→ View report

Current Status of the Highest-GHz-Frequency RFID Systems (Also Highest-Frequency RFIC)

Mentor:Prof. S. Kar, EE Dept., IIT Kanpur

Compiled a report dealing with the technicalities & difficulties in the use of GHz frequency for RFID Systems.

→ View report

Design of Digital Security Code Lock System using Atmega8 Microcontroller

Mentor:Electronics Club, IIT Kanpur.

Our team of three students designed a Digital Security Code Lock System using Atmega8 microcontroller, programmed in C as well as Assembly Language which operates on digital lock using the 16bit LCD display.

→ Report not available!

Israel-Palestine Conflict and Humanitarian Crisis

Mentor:Prof. Munmun Jha, HSS Dept., IIT Kanpur

Report compiled to investigate the history behind the Israel - Palestine conflict and how it relates to humanitarian crisis and human rights violation especially in Gaza strip.

→ View report , → View ppt

Suicides by Farmers in India-Economical or Psychological Reasons?

Mentor:Prof. K. Ravi Priya, HSS Dept., IIT Kanpur

Report compiled by our team of three students aimed at investigating the psychological reasons for the suicides by farmers in India besides economical reasons.

→ View report

Multi Storey Car Parking System

Mentor:Prof. K. Ravi Priya, HSS Dept., IIT Kanpur

Our team under my leadership built a model of mechanism to implement multi storey car parking system.Project successfully completed in Mechanical Engineering Lab.

→ View image

Kattwyk Bridge Model

Mentor:Prof. K. Ravi Priya, HSS Dept., IIT Kanpur

Our team under my leadership built a model of Kattwyk Bridge, Hamsberg, Germany in Material and Matellurgical Lab using arc welding.

→ View image , → View report

Skills

In past time I have tried learning few of these things of my own.

75

HTML5 / CSS3

Got inspired a lot from upcoming web design technology
75

jQuery/Javascript

Tried quite a bit in implementing on various projects
80

PHP / MySQL

Started web coding from basics in PHP & MySQL.
50

Python / Django

Invested short stint in creating portal for Relcy.com
80

C++ / Java

Learned from High School to Grad School
75

Perl / TCL

Bread & Butter in simplifying daily tasks at work.
90

HSPICE / Verilog

Languages that satiate my thirst for Electrical Engineering.
80

MATLAB / Labview

Tools I love most for complex engineering problems.
90

Cadence / ICC

Bread earner tools in daily job.

Portfolio

Projects involved with in past.

Awards

“I don't fly any awards at the house. Any award you get is usually for something you've done in the past. And I like to keep looking forward.”  -  Garth Brooks

2011-

Intel


Product Division's Highest Honor “Division Recognition Award'15” for exceptional contribution in debugging Knights Family product, bringing to life memory interface on First Silicon (A0), despite numerous challenges with this first generation memory.

Intel's Highest Honor “Intel Achievement Award'15” to entire team for exceptional performance and pushing the envelope for I/O industry.

Benefactor of IIT Kanpur with setting up “Nirmala & Ashok Keshri Scholarship” in 2014.

2009-2011

Stanford


Recipient of prestigious John Linvill Fellowship, Stanford University for the academic year 2009-2010 .

Best project for Lowest Energy Design with Minimum Area Overhead in VLSI Systems Course at Stanford University in the academic session Fall'09.

Best project for Best Robust Amplifier Design with Least Power Consumption in Analog Circuit Design Course at Stanford University in the academic session Fall'09.

2005-09

IIT Kanpur


Nominated for Best B.Tech Project in Electrical Engineering Department at IIT Kanpur.

Recipient of Academic Excellence Award for the 2 consecutive Academic Years 2005-2006 & 2005-2006, at IIT Kanpur for excellent academics.

Nominated for Best B.Tech Project in Electrical Engineering Department at IIT Kanpur.

Recipient of Academic Excellence Award for the 2 consecutive Academic Years 2005-2006 & 2005-2006, at IIT Kanpur for excellent academics.

Scored SPI (Semester Point Index) =10.0/10.0 in 4 consecutive Semesters (3rd, 4th, 5th & 6th).

Recipient of Sri Temasek Scholarship, IIT Kanpur for the year 2006-07 for outstanding performance in academics.

Recipient of Dr. D. R. Bhagat Scholarship, IIT Kanpur for the year 2007-08 for excellent academic record throughout the year.

span>Represented IIT Kanpur in 6th Indo-German Winter Academy'07, held at IIT Guwahati.

Represented IIT Kanpur in 1st Indo-US Research Academy'08, held at Pune.

Scored All India Rank: 270 in IIT-JEE, 2005 (Out of approx. 0.175 million students all over the country).

Scored State Rank: 1 in DCE-CEE, 2005 (Delhi College of Engineering Combined Entrance Exam, 2005,(Out of approx. 0.055 million students)).

Contact

You can contact me through phone/email. I won't bite you.

Contact details

626 Hollenbeck Ave, Unit#3,
Sunnyvale, CA-94087, USA

+1 (650) 644 7450

piyushkeshri@gmail.com

www.piyushkeshri.net

Blog

Dilligrocery-Online Grocery Store Online Grocery Shopping in Delhi, NCR India - Retail sector in India and specifically Online Retail in India is at its nascent stage presently and is yet to see phenomenal improvements in various aspects of Online Shopping ranging from Quality assurance, better customer service, and affordable prices to improved customer experience overall. With such objectives & milestones ahead, a local renowned Kirana/ Grocery 

Continue Reading →