Piyush Keshri
Product Lead, Entrepreneur, & Engineer
My love for technology, finance, and entrepreneurship has convinced me to wear different hats to solve real-world problems and create an impact.
Download Printable Resume
Things I have been upto that are worth mentioning here :)
Led Commerce strategy & roadmap powering $4B+ annual revenue across all consumer businesses & devices (web, mobile apps)
Introduced growth initiatives driving $50M+ incremental annual revenue by improving conversion through optimizing checkout & payments and expanding payments globally by supporting more currencies (60+), local cards, & alternative payment methods
Drove $20M+ with better member retention by building ML-driven payment routing & smart scheduling of recurring transactions
Directed & scaled engineering team from 9 to 43+ engineers in last 2 years to build Commerce as state-of-art, self-serve platform to accelerate go-to-market for consumer & enterprise products - Checkout as a service; self-serve catalog, & Tax systems
Represented LinkedIn in industry-wide Merchants Payments Roundtable semi-annually to discuss industry outlook
Built niche eCommerce with largest nuts & dry fruits (140+) varieties serving across India; increased sales 4X by expanding logistics and servicing across India; transformed traditional family grocery store into an omnichannel brand
Increased profit margins by 2X by introducing quality-focused private label brand with inventory & marketplace-based model
Expanded distribution through India’s largest online marketplace, Flipkart and increased sales by 50%
Led market entry for consumer point-of-sale financing for in-store purchases; strategized product-market fit through in-house market research on consumer behavior; conducted early customer interviews. Coordinated team of 18+ design, engineering, sales, marketing & legal and compliance experts to build UX prototypes, define product engineering requirements, design marketing collaterals, and go-to-market plan for product launch. Managed Growth and Data Insights team; identified actions to accelerate consumer acquisition growth by 10x for invoice financing
Drove product-strategy to build $60 million Brand advertising business, for marketers focused on brand-safety in online ads. Leveraged machine learning to dynamically score websites on brand-safety. Directed engineering, sales & marketing teams across US, UK, to build programmatic advertising catering to premium online portals
Secured 2nd prize in Quantcast Intern Hackathon Challenge.
Designed Resistor Compensation block involving Comparator design, Tx, vref Ladder. Worked on clock distribution in Rx/Tx clusters, Sideband Rx & Local Clock Macros. Leveraging scripting languages (Perl,Tcl) in evaluating circuits for corner cases and variations.
Providing relevant web-content to users based on users’ social-interest graphs.
Fun I was having outside classes while I was at school!
Analog Front End Design for Bidirectional Communication On 10m coaxial cable @ 3Gbps. Design Blocks - CML Driver, Z-network Replica, Echo Canceller, and Active Equalizer. Application - Automotive Infotainment Systems – Audio, Video HD Displays.
Analyzed & designed highly Power Efficient CMOS Thyristor based Ring Oscillators. Application: DC-DC converters in Laptop Power Supplies.
Market analysis of the WiMAX System and Designing of Transceiver Circuit on PCB for the 5-5.9 GHz and 2-3 GHz frequency ranges.
Our team of three students designed a Digital Security Code Lock System using Atmega8 microcontroller, programmed in C as well as Assembly Language which operates on digital lock using the 16bit LCD display.
Few moments of imparting knowledge on other side of podium!
"Modeling Customer Data to grow business - Madison Reed". Summary of 6-weeks of intense work by a team of 6 multi-disciplinary students exploring and modelling customer data for Madison Reed and defining actions for the firm to grow business. Madison Reed is a premium, direct-to-consumer hair color product. The proprietory nature of the analysis limits sharing to a generic summary.
→ View report"Maximising incident power absorption in multijunction Solar Cells". The project and the presentation is based on determining the optimum band gap of the materials for single/double and triple junction solar cells to maximise the photon absorption by the multi junction solar cells to optimize the efficiency.
→ View report"Towards Highly Efficient Monolithic DC-to-DC to Converter". The presentation gave an overview on the state-of the-art of monolithic DC/DC converters, with low power, high efficiency, high switching frequency in (MHz) for a completely monolithic integrated switch-mode power converter.
→ View pptHard earned Sweat that resulted in a Degree at last (almost :D ).
Director’s List (top 10% of class of 2018)
GMAT - 760 (99th Percentile)
Teaching Assistant for two Professional courses
VP Leadership - Cluster Council; Startup Chair - Wharton India Economic Forum; Member of Tech Club, E-Club, FinTech Club
CGPA - 3.92/4.0
Cleared Qualifiers for PhD Program in Electrical Engineering in Jan. 2011 with Rank 26 at Stanford University and took leave from PhD program.
CGPA - 9.7/10.0
Percentage Obtained: 91.4 %
Percentage Obtained: 89.4 %
Things I have been upto that are worth mentioning here :)
India’s cashless drive through demonetization and its impact on FinTech Landscape
Prof. Ethan Mollick, Wharton, Jan'17-May'17
Analyzed the impact of Demonetization announced by Indian Government on Nov. 8th, 2016 on the Fintech sector and the required steps to push cashless drive within country.
VC Term-Sheet Negotiations
MGMT804, Wharton, Jan'17-May'17.
As a founding team of a Hi-Tech firm needed to negotiate the term-sheets from two VC firms and decide the favorable investment for the firm.
Wintel - Recreating PC Revolution in VR
MGMT 712, Jan'17-May'17
Explored the trends in VR industry and how hypothetical Joint Venture between Windows and Intel can revolutionize the VR industry, similar to PC world.
Who will win Autonomous Vehicles war?
MGMT 731, Sep'17-Dec'17
Explored the entry of incumbent (Ford), innovator (Tesla), and disruptor (Waymo) in Autonomous Vehicles industry and who will win through the lens of Technology Strategy.
Optimization of Ammunition Distribution for Military Training
OIDD 612, Sep'17-Dec'17
Helping Cavalry Regiment in Eastern Europe to optimize ammunition distribution for training purposes, using Linear Optimization.
Design of 5-Bit Time-Interleaved ADC
EE315B,Stanford,Sep'10-Nov'10.
Each ADC operates at 400MS/s and can sample up to 1.6GHz signal. Clocked Bootstrap Switch & Double Tail Latch Type Sense Amplifier based Comparator.
Comparative Study of Trans impedance Amplifier
Prof. Boris Murmann, Stanford- Apr’10-May’10
• Analyzed trade-offs for various topologies specifically– Capacitive feedback, Resistive feedback and Integrator-Differentiator approach For MEMS Resonators for GSM Systems.
Design of 3.5 GHz Wideband Trans impedance Amplifier
EE214, Stanford- Jan’10-Mar’10
For high speed Optical Communication Systems using 180nm CMOS Technology. Implemented Cherry Hooper Architecture for High Gain & Bandwidth.
Analysis and Design of High Frequency Transceiver LNA-Mixer
EE314, Stanford- Apr’10-May’10
For WiFi Chipsets at operating frequency of 2.45GHz & Bandwidth of 200MHz. Power Gain 30dB and IIP3 ~ - 20dBm using 90nm CMOS Technology. Architecture - Inductively Degenerated Cascoded LNA & Double Balanced Active Mixer.
VLSI Implementation of DNA Sequencing
EE272, Stanford- Apr’10-May’10
Synthesized, placed and routed complete ASIC design using 90nm CMOS Technology. Employed low power Verilog coding techniques with hardware reusage and parallelism.
Hardware Improvements for Micropolygon Rasterization
EE271, Stanford- Sep’09-Nov’09
Optimized throughput & power by 3.5X, using - Triangle Merging, backface Culling. Special Acknowledgement for “Lowest Energy &Minimum Area Optimized Design".
Design of High Speed & low power SRAM Memory
EE313, Stanford- Jan’10-Mar’10
Designed a 64kB complete SRAM memory using 45nm CMOS Technology. Significant Techniques – Divided Wordline, partitioned Bitline, variable delay SAE signal.
Designing a High Speed Signaling System
EE273, Stanford- Jan’10-Mar’10
To connect line modules in a High Speed Router operating at 40Gbps. Employed a pair of Central Crossbar switches with backplane architecture.
Optical Character Recognition for Handwritten Hindi
CS229, Stanford- Sep’10-Dec’10
Various feature extraction and classification algorithms explored. Best results obtained using One-against-All SVM & extracting features using HOG process.
Hardware Improvements for Rasterizer Design
EE Dept., Stanford University
The goal of the project is to get a render speed of 500 Million μPolys/sec while consuming as little power and area as possible. The baseline rasterizer provided runs with a clock period of 1.05 ns and has a throughput of 0.083 μPolys/cycle( or 79 Million μPolys/sec). We were able to obtain a throughput of 550 Million μPolys/sec. Hence, our design meets the throughput requirements, has an optimized FOM value and also has power and area dissipation within the specified budget of 300mW and 1mm2 respectively. Our implementation strategy has received the "Lowest Energy Design with Minimum Area Overhead" award within the complete class and have given special presentation over the strategies being followed by us. (NOTE: Video Link for the presentation will be soon uploaded).
Amplifier Design for Pore Based Bio-Sensor Chip
Prof. Robert Dutton , EE Dept., Stanford University.EE Dept., Stanford University
The project is based on Designing the amplifier for pore based Bio-Sensor chip with the required specifications (as mentioned in design problem statement). The robust design for the amplifier circuit has been implemented and simulated in the HSPICE. Our design has received the "Best Robust Design with Least Power Consumption" award within the complete class.
B.Tech Project: Networked Service Request System (NSRS)Networked RFID System (NRS) for Remote Services
Prof. S. Qureshi, EE Dept., IIT Kanpur.IIT Kanpur – July’08-Apr’09
Designed Complete Hardware-Software platform for requesting emergency services. Integrated RFID & GSM Technology with the Central Web Based Database System. Developed complete IVR System & Web Platform to connect to central Database.The project is based on Designing Networked RFID System (NRS) ",which is the extension of the project "Remote Gas Service" which has filed the National patent on April'08. The project is aimed at Designing a networked RFID system which integrates RFID reader & Web interface with the Web based Centralized Database Management System. The system has been extended and has been integrated with the wireless access using GSM modules & also using wired telephone lines to form Interactive voice response system to access Database. The project has been aimed with the objective of implementation in remote and rural areas to provide emergency services through efficient reliable system. The project is soon to be implemented within the campus for initial phase testing.
Analysis of High Speed Low Power Flip Flops
Mentor:Prof. S. Qureshi, EE Dept., IIT Kanpur.Prof. Robert Dutton , EE Dept., Stanford University.EE Dept., Stanford University
The project is based on designing the compensation circuit for the CMOS thyristor based Current Starved Ring Oscillator design operating at 100kHz to reduce the Temperature Sensitivity of the circuit. Project is based on the analysis of the performance of different high speed low power flip flops such as Hybrid Latch Flip Flop, Sense Amplifier based Flip Flop, Semi- Dynamic Flip Flop, Master Slave Flip Flop, Clock Gated Master Slave Flip Flop and other modified designs of Sense Amplifier based Flip Flops.
Report Not Available!
Design of Compensation circuit to neutralise Temperature Dependence of the Ring Oscillator Design based on CMOS Thyristor Design
Course Project
Mentor:Prof. S. Qureshi,
EE Dept., IIT Kanpur
The project is based on designing the compensation circuit for the CMOS thyristor based Current Starved Ring Oscillator design operating at 100kHz to reduce the Temperature Sensitivity of the circuit. The technology used is 0.18micron.
Maximising incident power absorption in multijunction Solar Cells
1st Indo-US Research Academy, Pune, India (07-11th October'08)
Mentor:Prof. S.S.K Iyer, EE Dept., IIT Kanpur
The project and the presentation is based on determining the optimum band gap of the materials for single/double and triple junction solar cells to maximise the photon absorption by the multi junction solar cells to optimize the efficiency.
Towards Highly Efficient Monolithic DC-to-DC to Converter
6th Indo-German Winter Academy, Guwahati, India (13th-19th Dec.'07) Mentor:Prof. Heiner Ryssel, University of Erlangen.
Contributed presentation in 6th Indo-German Winter Academy-2007, held from 13th-19th December’07 at IIT Guwahati. The presentation gave an overview on the state-of the-art of monolithic DC/DC converters, with low power, high efficiency, high switching frequency in (MHz) for a completely monolithic integrated switch-mode power converter.
Dynamics of Mobius Transformations and Image Compression
Prof. G.P. Kapoor, Mathematics Dept., IIT Kanpur
The presentation is based on exploring the dynamics of mobius transformations and image compression technique using fractals. Fractal Image Compression technique can be used for Image Compression effectively reduces size of the image file from few MHz to few kHz.
Current Status of the Highest-GHz-Frequency RFID Systems (Also Highest-Frequency RFIC)
Mentor:Prof. S. Kar, EE Dept., IIT Kanpur
Compiled a report dealing with the technicalities & difficulties in the use of GHz frequency for RFID Systems.
Design of Digital Security Code Lock System using Atmega8 Microcontroller
Mentor:Electronics Club, IIT Kanpur.
Our team of three students designed a Digital Security Code Lock System using Atmega8 microcontroller, programmed in C as well as Assembly Language which operates on digital lock using the 16bit LCD display.
→ Report not available!
Israel-Palestine Conflict and Humanitarian Crisis
Mentor:Prof. Munmun Jha, HSS Dept., IIT Kanpur
Report compiled to investigate the history behind the Israel - Palestine conflict and how it relates to humanitarian crisis and human rights violation especially in Gaza strip.
Suicides by Farmers in India-Economical or Psychological Reasons?
Mentor:Prof. K. Ravi Priya, HSS Dept., IIT Kanpur
Report compiled by our team of three students aimed at investigating the psychological reasons for the suicides by farmers in India besides economical reasons.
Multi Storey Car Parking System
Mentor:Prof. K. Ravi Priya, HSS Dept., IIT Kanpur
Our team under my leadership built a model of mechanism to implement multi storey car parking system.Project successfully completed in Mechanical Engineering Lab.
Kattwyk Bridge Model
Mentor:Prof. K. Ravi Priya, HSS Dept., IIT Kanpur
Our team under my leadership built a model of Kattwyk Bridge, Hamsberg, Germany in Material and Matellurgical Lab using arc welding.
In past time I have tried learning few of these things of my own.
“I don't fly any awards at the house. Any award you get is usually for something you've done in the past. And I like to keep looking forward.” - Garth Brooks
Finalist - Citadel Data Open Championship 2017. Represented University of Pennsylvania Team for the final round of challenge in NYSE.
Winner - Stripe Product Challenge, INSEAD Singapore.
1st Prize - Citi Ventures FinTech Challenge , Wharton.
Winner - Avis Data Visualization Challenge, Wharton.
Top finalist for Class of 2018 Big Idea Innovation tournament, Wharton.
Product Division's Highest Honor “Division Recognition Award'15” for exceptional contribution in debugging Knights Family product, bringing to life memory interface on First Silicon (A0), despite numerous challenges with this first generation memory.
Intel's Highest Honor “Intel Achievement Award'15” to entire team for exceptional performance and pushing the envelope for I/O industry.
Benefactor of IIT Kanpur with setting up “Nirmala & Ashok Keshri Scholarship” in 2014.
Recipient of prestigious John Linvill Fellowship, Stanford University for the academic year 2009-2010 .
Best project for Lowest Energy Design with Minimum Area Overhead in VLSI Systems Course at Stanford University in the academic session Fall'09.
Best project for Best Robust Amplifier Design with Least Power Consumption in Analog Circuit Design Course at Stanford University in the academic session Fall'09.
Nominated for Best B.Tech Project in Electrical Engineering Department at IIT Kanpur.
Recipient of Academic Excellence Award for the 2 consecutive Academic Years 2005-2006 & 2005-2006, at IIT Kanpur for excellent academics.
Nominated for Best B.Tech Project in Electrical Engineering Department at IIT Kanpur.
Recipient of Academic Excellence Award for the 2 consecutive Academic Years 2005-2006 & 2005-2006, at IIT Kanpur for excellent academics.
Scored SPI (Semester Point Index) =10.0/10.0 in 4 consecutive Semesters (3rd, 4th, 5th & 6th).
Recipient of Sri Temasek Scholarship, IIT Kanpur for the year 2006-07 for outstanding performance in academics.
Recipient of Dr. D. R. Bhagat Scholarship, IIT Kanpur for the year 2007-08 for excellent academic record throughout the year.
span>Represented IIT Kanpur in 6th Indo-German Winter Academy'07, held at IIT Guwahati.
Represented IIT Kanpur in 1st Indo-US Research Academy'08, held at Pune.
Scored All India Rank: 270 in IIT-JEE, 2005 (Out of approx. 0.175 million students all over the country).
Scored State Rank: 1 in DCE-CEE, 2005 (Delhi College of Engineering Combined Entrance Exam, 2005,(Out of approx. 0.055 million students)).
You can contact me through phone/email. I won't bite you.
1267 Coronado Dr, Apt 4,
Sunnyvale, CA-94086, USA
+1 (650) 644 7450